Techniques to allow the PA to operate in its most efficient region close to the 1dB compression point, with lower PAPR, can reduce the RF power consumption significantly.
Commonly used techniques include Digital Pre-Distortion (DPD) which pre-compensates the PA's non linearity, and Crest Factor Reduction (CFR) which clips the peaks of the signal to keep the error vector magnitude within 3GPP limits. DPD and CFR algorithms can be executed in a Digital Front End (DFE) typically implemented in the basestation's radio module.
A conventional hard-wired DFE is limited in its ability to support various frequency bands, air standards and types of PA. To overcome these challenges, LSI's SoftDFE® technology presents an agile solution that allows engineers to develop application-specific, power-efficient RF DFE modules for the PA.
It is able to support all the algorithms such as DPD and CFR required for a DFE to increase the amplifier's efficiency to over 50%.
Moreover, Soft DFE is programmable allowing the algorithms to be optimised, and also updated in the field if necessary - more readily than is possible with an alternative FPGA-based implementation.
The LSI Soft DFE block can be implemented in a standalone device, such as may be used in a remote radio head or the radio card of a macro basestation, or can be integrated as part of a larger System on Chip (SoC) together with a pico basestation's baseband unit (BBU) designed around LSI's high-efficiency Axxia® baseband processor architecture.
Better Baseband Processing
A typical basestation BBU is responsible for Layer-1, Layer-2 and Layer-3 processing, and supports wireless protocols such as LTE, LTE-A, WCDMA (and WiFi in small cell basestations). The choices open to equipment designers, as far as baseband processing is concerned, have typically been either a programmable FPGA-based solution or a custom ASIC and programmable DSPs.
More recently, large integrated multi- core CPU and DSP devices operating at a high clock frequency have been positioned as a baseband processing solution.
The established FPGA or ASIC options tend to force designers to trade-off the adaptability that an FPGA provides, for example to support emerging standards and protocols, against the performance and efficiency advantages traditionally offered by a custom ASIC-based solution. However, neither of these approaches satisfies every need for high performance, flexibility and energy efficiency.
LSI's Axxia technology introduces a new architecture that satisfies the increasing performance demands brought about by ubiquitous mobile data services while providing the flexibility and scalability to adapt and optimise the baseband processing and support efficient power management.
In addition, the architecture is scalable to address the processing demands both of macrocells and of smaller cells used to improve overall network efficiency.
Combining flexibility with high data-processing performance the platform utilises up to 16 ARM® Cortex™-A15 cores, as shown, which creates an extremely power efficient solution for data-plane processing tasks.
These cores are combined with LSI's Virtual Pipeline™ technology which comprises highly efficient hardware-based network accelerators for high-performance data-plane processing.
These accelerators include a multi-protocol packet processing engine capable of throughput up to 50Gbit/s, a 20Gbit/s security engine, and dedicated traffic management, content inspection and intelligent packet switch functions.
The Axxia platform represents the first instantiation of ARM's high-performance CoreLink™ CCN-504 QoS-aware low-latency coherent memory interconnect. This interconnect is used to link all of the main processing and memory elements of the SoC.
LSI's Virtual Pipeline technology and dedicated acceleration engines enable an extremely power-efficient solution compared to devices that just use large numbers of CPU cores. The CPU cores are typically run at high frequencies, hence consuming large quantities of power, to perform data-plane tasks to which they are not ideally suited.
Moreover, the Virtual Pipeline acceleration engines are designed to be modular thus enabling the processor to be scaled to higher performance levels without excessively increasing power consumption.
Scaling the number of Cortex-A15 control-plane cores and Virtual Pipeline resources of the Axxia architecture enables engineers to create a suitable system-on-chip solution for any size basestation, from a 3G or LTE macrocell to the smaller cell sizes used in a heterogeneous architecture.
The number of physical-layer interfaces and digital functions integrated on chip can also be optimised. In addition, OEMs have the flexibility to add proprietary functions for baseband processing as fixed function hardware blocks, programmable DSP cores and software, to customise the SoC or increase integration.
Support for software for common transport and security protocols such as IPSec, IPV4, IPV6 and LTE MAC is already provided, giving extra flexibility to adjust power and performance by offloading further data-plane functions.
Integrated Baseband-Unit SoC
Together, LSI's Soft DFE technology and Axxia processing platform can achieve up to a 50% reduction in the power consumed by the RF and baseband circuitry of a 3G or LTE macrocell.
When combined with the efficiency improvements provided by the HetNet network architecture, taking advantage of smaller-scale Axxia basestation processors, a significant increase in overall power efficiency can be achieved – giving network operators valuable extra control over operating expenses.
Conclusion
As the popularity of wireless Internet access continues to grow explosively across the globe, the power consumed by cellular basestations represents a rapidly growing proportion of total network power consumption. It is vital for network operators to improve the efficiency of their networks and basestations.
Complementing the migration of the network to a more efficient HetNet architecture, an innovative basestation processor architecture that delivers an enhanced combination of hardware efficiency with the flexibility and adaptability of a reprogrammable solution can help regain control over the spiralling power consumption of today's basestation RF and baseband circuitry.
- Ed Saba is product manager of the Axxia Communication Processor family within the Networking Components Division of LSI Corporation.
- Steve Vandris is director of Strategic Planning for the Networking Components Division of LSI Corporation.
