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Samsung rival plans monstrously fast SSD that can reach 10 million IOPS using SLC NAND

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Kioxia's new drive will use XL-Flash and a specially developed controller

A Kioxia building
(Image credit: Kioxia)
  • Kioxia details its plans for a new SSD for AI workloads reaching 10 million IOPS
  • IOPS measures how quickly a storage device can handle small, random requests
  • New drive uses XL-Flash, a type of SLC NAND, and a new in-house controller

Kioxia has unveiled plans for a new SSD it says could hit an impressive 10 million IOPS, a level of performance aimed squarely at the demands of AI-driven systems.

The SSD will use XL-Flash, a type of single-level cell (SLC) NAND, combined with a new in-house controller.

A Kioxia spokesperson told TechPowerUp, “We’re taking our ultra-fast XL-Flash memory chips, which use single-level cells, and pairing them with a completely new controller… We're targeting over 10 million IOPS, and we plan to have samples ready by the second half of 2026.”

Difference between IOPS and GBps

IOPS, or input/output operations per second, measures how quickly a storage device can handle small, random requests, particularly important in AI and server applications where fast access to small files is key.

This is different from GBps, which refers to the actual data transfer speed and is used to measure how fast large files can be read or written.

A drive with high GBps might excel in video editing or large file transfers, but for machine learning tasks where thousands of small data packets are read or written constantly, high IOPS matters more.

Kioxia’s approach to next-gen storage includes not just one-off projects but a wider effort to meet varied use cases. Its CM9 series, which is sampling to customers now, focuses on speed and reliability to match high-end GPUs used in AI, while the LC9 series delivers massive 122TB capacities for large databases.

Behind these products is the 8th generation BiCS FLASH, which introduces CBA tech to boost performance and efficiency.

Kioxia is also preparing future flash memory generations using two methods. The first will add more layers for capacity, while the second blends new CMOS designs with older cell structures to keep investment costs in check.

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Wayne Williams
Wayne Williams
Editor

Wayne Williams is a freelancer writing news for TechRadar Pro. He has been writing about computers, technology, and the web for 30 years. In that time he wrote for most of the UK’s PC magazines, and launched, edited and published a number of them too.

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